Over the past several years, the computer industry has experienced a remarkable evolution in the architecture of technical and office computing systems. Distributed "smart" workstations have increasingly replaced the simple "dumb" terminal attached to a mainframe or microcomputer. These "smart" workstations are, themselves, computers having local processing ability and local memory storage. Such "smart" workstations comprise part of a larger network, which includes a wide variety of processors, data storage and communication devices, and other peripherals.
A workstation network generally consists of individual user workstations (referred to as "clients") and shared resources for filing, data storage, printing and wide-area communications (referred to individually as "servers"). The clients and servers are interconnected along a local area network ("LAN"), such as an ethernet. Multiple ethernets may be connected to one another by a backbone ethernet.
Clients along an ethernet are typically connected to a server providing the clients with data and storage facilities. Servers that primarily provide for file storage access are referred to as "file servers". A conventional server might include a central processing unit ("CPU") coupled to the ethernet. The CPU itself is coupled to a primary memory device. Both the CPU and the primary memory device are connected to a conventional input-output device ("I/0"), such as a bus. Using the bus, the CPU may communicate with other devices such as disk controllers, for mass storage, or other peripheral devices.
Although processor technology and performance has increased significantly in recent years, input/output performance has not commensurately improved to date. Thus, although the processing performance capabilities of the CPU are considerable, the overall performance of the system is less formidable due to the lower performance threshold of I/O embodied in the bus.
The level of performance of any bus is largely determined by the time required to execute data transfer transactions across the bus. If the transaction time for a given transaction across the bus can be optimized to the shortest period of time possible, the bus will be capable of handling more transactions in a given period of time. Hence, performance is increased as the bus is capable of handling a greater number of transactions during a given period of time.
The VME backplane bus (hereinafter "VMEbus") is one of the most popular I/O bus systems presently in use. The VMEbus is widely implemented and standard throughout the industry. To this end, the Standards Committee of the Institute of Electrical and Electronics Engineers ("IEEE") has formulated and published VMEbus standards in a publication entitled VMEbus Specification Manual, revision D1.2. (hereinafter "the VMEbus standard"), which is hereby incorporated by reference.
The standard VMEbus interface system consists of backplane interface logic, four groups of signal lines referred to as "buses," and a collection of functional modules which communicate with one another using the signal lines. The four buses are the data transfer bus ("DTB"), arbitration bus, priority interrupt bus and utility bus. The present application is principally concerned with the DTB.
The DTB allows "masters," which are functional modules, such as the CPU or other intelligent controllers connected to the VMEbus, that initiate DTB cycles, to direct the transfer of binary data between themselves and "slaves." A "slave" is a functional module, such as primary memory, which detects DTB cycles initiated by a "master" and, when those cycles specify its participation, transfers data to or receives data from its "master."
There are seven DTB cycles which a "master" may implement on the DTB: READ, WRITE, BLOCK READ, BLOCK WRITE, READ-MODIFY-WRITE, ADDRESS ONLY, and INTERRUPT ACKNOWLEDGE CYCLE.
In a READ cycle, one, two, three or four bytes of parallel data are transferred across the DTB from master to slave. The READ cycle begins when the master broadcasts an address and an address modifier and places data on the DTB. Each slave captures the address and address modifier and determines whether it is to respond to the cycle. The intended slave recipient retrieves the data from its internal storage and places the data on the DTB, acknowledging the data transfer.
In a WRITE cycle, one, two, three or four bytes of parallel data are transferred across the bus from a master to a slave. The cycle commences when the master broadcasts an address and address modifier and places data on the DTB. Each slave on the bus captures the address and address modifier and determines whether it is to respond to the cycle. The intended slave(s) stores the data and acknowledges the transfer.
The BLOCK READ cycle is a DTB cycle used to transfer a block of one to two-hundred fifty-six bytes from a slave to a master. The BLOCK READ transfer is accomplished using a string of one, two or four byte-wide (i.e., 8, 16, or 32 bit-wide data words) data transfers. Once the block transfer is started, the master does not release the DTB until all of the bytes have been transferred. The BLOCK READ cycle differs from a string of READ cycles in that the master broadcasts only one address and address modifier at the beginning of the cycle. The slave increments the address on each transfer in order that the data for the next transfer is retrieved from the next higher location.
The BLOCK WRITE cycle, like the BLOCK READ cycle, is a DTB cycle used to transfer a block of one to two-hundred fifty-six bytes from a master to a slave. The BLOCK WRITE transfer is accomplished using a string of one, two or four byte-wide data transfers. Once the block transfer is started, the master does not release the DTB until all of the bytes have been transferred. The BLOCK WRITE cycle differs from a string of WRITE cycles in that the master broadcasts only one address and address modifier at the beginning of the cycle. The slave increments the address on each transfer in order that the data for the next transfer is retrieved from the next higher location.
The READ-MODIFY cycle is a DTB cycle used to both read from and write to a slave location without permitting another master access to the slave location.
The ADDRESS-ONLY cycle consists only of an address broadcast. Data is not transferred. Slaves do not acknowledge ADDRESS-ONLY cycles and the master terminates the cycle without waiting for an acknowledgement.
It should be noted that this differs from "synchronous" systems in that in totally "synchronous" systems the response of the slave is irrelevant. This initiation of a DTB cycle is referred to in the art as "handshaking." After a master initiates a data transfer cycle it waits for the designated slave to respond before finishing the cycle. The asynchronous nature of the VMEbus allows a slave to take as long as it needs to respond. The VMEbus requires four propagations across the DTB to complete a single handshake sequence. If a slave fails to respond because of a malfunction or if the master accidentally addresses a location where there is no slave, the bus timer intervenes allowing the cycle to be terminated.
The VMEbus standard specifies the use of location monitors, which are on the functional modules, to monitor data transfers over the DTB. Each operates to detect accesses to the locations it has been assigned to watch. When an access to one of these assigned locations occurs, the location monitor typically signals its on-board processor by means of an interrupt request signal. In such a configuration, if processor A writes into the global VMEbus memory monitored by processor B's location monitor, processor B will be interrupted.
The DTB includes three types of lines: addressing lines, data lines and control lines.
Masters use address lines numbers 2 through 31, denoted as A02 through A31, to select a four-byte group to be accessed. Four additional lines, data strobe zero (DS0*), data strobe one (DS1*), address line number one (A01) and longword (LWORD*), are then used to select which byte locations within the four-byte group are accessed during the data transfer. The asterisk following the abbreviated line designation denotes that these lines are "active low" (i.e., considered "active" when driven low). Using these four lines, a master can access one, two, three or four-byte locations simultaneously, depending upon the type of cycle initiated.
The DTB includes six address modifier lines which allow the master to pass additional binary information to the slave during a data transfer. Sixty-four possible modifier codes exist, which are classified into each of three categories: defined, reserved and user defined. User defined codes may be used for any purpose which the user deems appropriate. Typical uses of the user defined codes include page switching, memory protection, master or task identification, privileged access to resources and so forth.
Thirty-two data lines, D00 through D31, actually transfer data across the bus. The master may simultaneously access up to four byte locations. When the master has selected the byte locations to be accessed, it can transfer binary data between itself and those locations over the data bus.
The DTB includes six control lines: address strobe (AS*), data strobe zero (DS0*), data strobe one (DS1*), bus error (BERR*), data transfer acknowledge (DTACK*), and read/write (WRITE*). The VME standard requires that the control lines be considered "active" when driven low.
A falling edge on the AS* line informs all slave modules that the broadcasted address is stable and can be captured.
DS0* and DS1*, in addition to their function in selecting byte locations for data transfer, also serve control functions. On WRITE cycles, the first falling edge of the data strobe indicates that the master has placed valid data on the data bus. On READ cycles, the first rising edge tells the slave when it can remove valid data from the DTB.
A slave will drive DTACK* low to indicate that it has successfully received the data on a WRITE cycle. On a READ cycle, the slave drives DTACK* low to indicate that it has placed data on the DTB.
The BERR* line is an open-collector signal driven low by the slave or the bus timer to indicate to the master that the data transfer was unsuccessful. For example, if a master tries to write to a location which contains Read-Only memory, the responding slave might drive BERR* low. If the master tries to access a location that is not provided by any slave, the bus timer would drive BERR* low after waiting a specified period of time.
WRITE* is a level significant line strobed by the leading edge of the first data strobe. It is used by the master to indicate the direction of data transfer operations. When WRITE* is driven low, the data transfer direction is from the master to the slave. When WRITE* is driven high, the data transfer direction is from the slave to the master.
The VMEbus standard sets forth a handshake which requires four separate propagations across the VMEbus. The master asserts DS0* and DS1* to initiate the data transfer cycle. The slave, in response to the master's assertion of DS0* and DS1*, asserts DTACK*. In response to the assertion of DTACK*, the master deasserts DS0* and DS1*. The slave, in response, deasserts DTACK* to complete the handshake. Each four of these propagations is required to accomplish the handshake.
The maximum transfer rate across a typical VMEbus is generally in the range of 20 to 30 megabytes per second. However, in situations where a great deal of data must be transferred very quickly from one device on the VMEbus to another device on the VMEbus or a large number of data transfers need to be made, this transfer rate can oftentimes be slow enough to result in processing delays. Accordingly, in order to maximize data transfer and processing efficiency, the transfer rate of data across the VME backplane bus should be increased.
A significant limitation to increasing the data transfer speed of the VMEbus, in addition to the limitations described above, is the ability to provide data to the bus at rates in excess of 20 to 30 megabytes per second. Typically, a conventional microprocessor, such as a Motorola 68020, and a standard peripheral DMA controller are used to drive a data burst onto the VMEbus. However, regardless of the actual peak data burst speed of the DMA controller, the overhead that must be performed both during and between data burst transfers by the microprocessor becomes a significant limiting factor. Consequently, while peak transfer rates of 40 megabytes per second are sometimes claimed, the actual average transfer rates for extended amounts of data is often much less than even 20 megabytes per second.